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Preliminary Technical Data
FEATURES
SFP reference design available Input sensitivity: 3 mV p-p 65 ps rise/fall times BW Select to support Multi-Rate 1x/2x/4x FC modules Optional LOS Output Inversion to support SFF CML outputs: 700 mV p-p differential Programmable LOS detector: 3 mV to 45 mV Rx signal strength indicator (RSSI): SFF-8472 compliant average power measurement Single supply operation: 3.3 V Low power dissipation: 160 mW Available in space-saving 3 x 3 mm 16-lead LFCSP Increased Temperature Range: -40oC to 95oC
3.3 V 4.25 Gb/s Limiting Amplifier ADN2892
The ADN2892 is a high gain, limiting amplifier optimized for use in Fibre Channel and GbE optical receivers. The ADN2892 accepts input levels of up to 2.0 V p-p differential and has 3 mV p-p differential input sensitivity. The ADN2892 provides the receiver functions of quantization and loss of signal (LOS) detection. The ADN2892 has an on-chip selectable filter to reduce the BW of the limamp to 1.5GHz in order to filter out the relaxation oscillation of legacy 1Gb/s Fiber Channel transmitters with CD lasers. The reduced BW will also allow for more optical Rx sensitivity margin at the lower data rates such as 1xFC and 1GbE in multi-rate modules. The limiting amplifier also measures average received power based on a direct measurement of the photodiode current with better than 1 dB of accuracy over the entire input range of the receiver. This eliminates the need for external average Rx power detection circuitry in SFF-8472 compliant optical transceivers. The ADN2892 limiting amplifier operates from a single 3.3 V supply, has low power dissipation, and is available in a spacesaving 3 x 3 mm 16-lead lead frame chip scale package (LFCSP).
APPLICATIONS
SFP/SFF/GBIC optical transceivers 1x/2x/4x Multi-rate Fibre Channel receivers LX4 WDM transponders
PRODUCT OVERVIEW FUNCTIONAL BLOCK DIAGRAM
ADN2882
+V
PD_VCC PD_CATHODE VREF
10k ADuC7020
Figure 1.
Rev. PrA.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
LOS_INV
ADN2892 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ........................................................................ 8 LIMAMP ....................................................................................... 8
Preliminary Technical Data
Loss of Signal (LOS) Detector .....................................................8 Received Signal Strength Indicator (RSSI) ................................8 Squelch Mode ................................................................................8 Applications Information .................................................................9 PCB Design Guidelines ................................................................9 Outline Dimensions ....................................................................... 11 Ordering Guide .......................................................................... 11
REVISION HISTORY
Revision A: Initial Version
Rev. PrA| Page 2 of 12
Preliminary Technical Data SPECIFICATIONS
VCC = VMIN to VMAX, VEE = 0 V, TA = TMIN to TMAX, BW_SEL = 1, unless otherwise noted. Table 1.
Parameter QUANTIZER DC CHARACTERISTICS Input Voltage Range Input Common Mode Peak-to-Peak Differential Input Range Input Sensitivity Input Offet Voltage Input RMS Noise Input Resistance Input Capacitance QUANTIZER AC CHARACTERISTICS Input Data Rate Small Signal Gain S11 S22 Random Jitter Deterministic Jitter Low Frequency Cutoff Power Supply Noise Rejection LOSS OF SIGNAL DETECTOR (LOS) LOS Assert Level LOS Hysteresis TBD LOS Assert Time LOS De-Assert Time RSSI Input Current Range RSSI Output Accuracy Gain Offset Compliance Voltage POWER SUPPLIES VCC ICC OPERATING TEMPERATURE RANGE CML OUTPUT CHARACTERISTICS Output Impedance Output Voltage Swing Output Rise and Fall Time LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage Input Current Min 1.8 2.1 3 100 205 50 0.65 1.0 1.0 51 -15 -15 5 10 30 45 TBD TBD 3.0 45.0 3 3 600 100 TBD TBD TBD 4.25 2.125 Typ Max 2.8 2.7 2.0 Unit V p-p V V p-p mV p-p V V rms pF Gb/s Gb/s dB dB dB ps rms ps p-p kHz dB mV p-p mV p-p dB dB ns ns A % % mA/mA nA V V mA C V p-p ps V V nA nA
ADN2892
Test Conditions/Comments @ PIN or NIN, dc-coupled DC-coupled PIN - NIN, ac-coupled PIN - NIN, BER 1 x 10-10
Single-ended
BW_SEL = 1 BW_SEL = 0 Differential Differential, f < 4.25 GHz Differential, f < 4.25 GHz Input > 10 mV p-p, 4.25Gb/s, PRBS 27 - 1 Input > 10 mV p-p, 4.25 Gb/s, PRBS 27 - 1 f < 10 MHz RTHRADJ = 100 k RTHRADJ = 0 4.25Gb/s, PRBS 27 - 1, RTHRADJ = 0 4.25Gb/s, PRBS 27 - 1, RTHRADJ = 100 k DC-coupled DC-coupled
5
1000 15 10 1.0 50
IIN 20 A IIN > 20 A IRSSI/IPD @ PD_CATHODE
VCC - 0.9 3.0 -40 3.3 50 +25 50 700 65
VCC - 0.3 3.6 +95
TMIN to TMAX Single-ended Differential 20% to 80%
600
800
2.0 0.8 -100 100
IINH, VIN = 2.4 V IINL, VIN = 0.4 V
Rev. PrA | Page 3 of 12
ADN2892
Parameter LOGIC OUTPUTS (LOS) VOH, Output High Voltage VOL, Output Low Voltage Min 2.4 0.4 Typ Max Unit V V
Preliminary Technical Data
Test Conditions/Comments Open drain output, 4.7 k - 10 k pull-up resistor to VCC Open drain output, 4.7 k - 10 k pull-up resistor to VCC
Rev. PrA| Page 4 of 12
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 s) Junction Temperature Rating 4.2 V VEE - 0.4 V VCC + 0.4 V -65C to +155C -40C to +95C 300C 125C
ADN2892
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for 4-layer PCB with exposed paddle soldered to GND. Table 3.
Package Type 16-lead 3 x 3 mm LFCSP JA 28 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 12
ADN2892 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PD_CATHODE PD_VCC RSSI_OUT SQUELCH
Preliminary Technical Data
AVCC PIN NIN AVEE
12 DRVCC 1 ADN2892A 2 Top View 11 OUTP 10 OUTN 3 9 DRVEE 4
THRADJ BW_SEL LOS_INV LOS 5 6 7 8
Figure 2. Pin Configuration
Note: There is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias.
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Exposed Pad Mnemonic AVCC PIN NIN AVEE THRADJ BW_SEL LOS_INV LOS DRVEE OUTN OUTP DRVCC SQUELCH RSSI_OUT PD_VCC PD_CATHODE Pad I/O Power Input Input Power Input Input Input Output Power Output Output Power Input Output Power Output Power Description Analog Power Differential Data Input Differential Data Input Analog Ground LOS Threshold Adjust Resistor Rate Select: BW_SEL = 0 for 1x/2xFC, BW_SEL = 1 for 4xFC LOS_INV=1 inverts the LOS output to be active low (for SFF). LOS Detector Output Output Buffer Ground Differential Data Output Differential Data Output Output Buffer Power Disable Outputs Average Current Output Power Input for RSSI Measurement Photodiode Bias Voltage Connect to Ground
Rev. PrA| Page 6 of 12
16 15 14 13
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
0.96 0.88 0.80 0.72 RSSI_OUT (mA) 0.64 0.56 0.48 0.40 0.32 0.24
04509-0-002
ADN2892
0.16 0.08 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
RSSI_IN (mA)
Figure 3. RSSI Output vs. Average PIN Photodiode Current
Figure 6. S11 Plot--TBD
LOS Trip Point -vs- RTHRADJ
50 40 mV 30 20 10 0 10 100 1000 ohms 10000 100000
Figure 4. LOS Trip Point vs. Threshold Adjust Resistor
70 60 50 40 30 20 10 0 100k
Figure 7.S22 Plot--TBD
SUPPLY-NOISE REJECTION (dB)
1M SUPPLY-NOISE FREQUENCY (Hz)
10M
Figure 5. Typical PSRR vs. Supply-Noise Frequency
Rev. PrA | Page 7 of 12
04509-0-010
ADN2892 THEORY OF OPERATION
LIMAMP
Input Buffer
The limiting amplifier has differential inputs (PIN/NIN), with an internal 50 termination. The ROSA (receive optical subassembly) is typically ac-coupled to the ADN2892 inputs (although dc coupling is possible). There is an on-chip, input offset compensation loop with a 30kHz low-frequency cutoff.
Preliminary Technical Data
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The threshold is set by a resistor connected between the THRADJ pin and VEE. When the input level drops below this threshold, the LOS output will assert to a logic 1. There is hysteresis built into the LOS circuit to prevent chattering at the LOS output. The LOS hysteresis is typically 5dB. The LOS output is an open-drain output that needs to be externally pulled up with a 4.7k-10k resistor. The LOS output active high by default which is compliant with the SFP and GBIC MSAs. There is an LOS_INV input which, when set to a logic 1, inverts the LOS output so that it is active low. This is in order to support the SFF MSA.
CML Output Buffer
The ADN2892 provides CML outputs, OUTP/OUTN. The outputs are internally terminated with 50 to VCC. The outputs can be kept at a static voltage by driving the SQUELCH pin to a logic high. The SQUELCH pin can be driven directly by the LOS pin, which automatically disables the LIMAMP outputs in situations with no data input.
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)
The ADN2892 has an on-chip RSSI circuit that automatically detects the average received power, based on a direct measurement of the PIN photodiode's current. The photodiode bias is supplied by the ADN2892, which allows a very accurate, onchip, average power measurement based on the amount of current supplied to the photodiode. The output of the RSSI is a current that is directly proportional to the average amount of PIN photodiode current. Placing a resistor between the RSSI_OUT pin and GND converts the current to a GND referenced voltage. This function eliminates the need for external RSSI circuitry in SFF-8472 compliant optical receivers.
BANDWIDTH SELECT
The ADN2892 has an on-chip selectable 4th order BesselThomson filter in order to support 1x/2x/4x Fiber Channel transceivers utilizing rate select. Setting the BW_SEL pin to logic 0 selects the on-chip filter which reduces the BW of the limamp to ~1.5GHz. This is sufficient to filter out the relaxation oscillation from legacy 1Gb/s Fiber Channel transmitters using CD lasers while still providing enough BW to be backwards compatible with 1x/2x FC multi-rate SFP modules that don't use the rate select function. Setting the BW_SEL pin to a logic 1 sets the bandwidth of the ADN2892 to the full BW of ~4.25GHz. This rate select protocol is compliant with SFF-8079 Rev 1.0
SQUELCH MODE
Driving the SQUELCH input to a logic high disables the limiting amplifier outputs. The SQUELCH input can be connected to the LOS output to keep the limiting amplifier outputs at a static voltage level anytime the input level to the limiting amplifier drops below the programmed LOS threshold.
Rev. PrA| Page 8 of 12
Preliminary Technical Data APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal performance.
ADN2892
greatly enhances the reliability of the connectivity of the exposed pad to the GND plane during reflow. Use of a 10 F electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2892 VCC pins. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 12, which supplies power to the high speed OUTP/ OUTN output buffers. Refer to the schematic in Figure 8 for recommended connections.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on Pin 9, which is the ground return for the output buffers. The exposed pad should be connected to the GND plane using filled vias so that solder does not leak through the vias during reflow. Using filled vias under the package
VCC C9 VCC 0.1F VCC
C5 C6
PD_CATHODE PD_VCC RSSI_OUT SQUELCH
R1
RSSI measurement to ADC C10
VCC
C7 C8
16 15 14 13
connect exposed pad to GND
C1 C2 ADN2882
AVCC PIN NIN
1 2 3 AVEE 4
THRADJ
12 11 10 9
DRVCC OUTP OUTN DRVEE C3 C4 To Host Board
BW_SEL LOS_INV LOS
5 6 7 8
VCC R3 4.7k - 10k on host board
C1-C4, C11: 0.01F X5R/X7R dielectric, 0201 case C5,C7,C9,C10,C12: 0.1F X5R/X7R dielectric, 0402 case C6, C8: 1nF X5R/X7R dielectric, 0201 case
C12
R2 to ADuC7020
Figure 8. Typical ADN2892 Applications Circuit
Rev. PrA | Page 9 of 12
ADN2892
PCB Layout
Figure 9 shows a recommended PC board layout. Use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, OUTP and OUTN. It is also necessary for the PIN/NIN input traces to be matched in length, and OUTP/OUTN output traces to be matched in length to avoid skew between the differential traces. C1, C2, C3, and C4 are ac coupling capacitors in series with the high speed I/O. It is recommended that components be used such that the pad for the capacitor is the same width as the transmission line to minimize the mismatch in the 50 transmission line at the capacitor's pads. It is recommended that the transmission lines not change layers through vias, if possible. For supply decoupling, the 1nF decoupling capacitor should be placed on the same layer as the ADN2892 as close as possible to the VCC pin. The 0.1uF capacitor can be placed on the bottom of the PCB directly underneath the 1nF decoupling capacitor. All high speed CML outputs are back-terminated on
Preliminary Technical Data
chip with 50 resistors connected between the output pin and VCC. The high speed inputs, PIN and NIN, are internally terminated with 50 to an internal reference voltage. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes.
Soldering Guidelines for Chip Scale Package
The lands on the 16 LFCSP are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the printed circuit board should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using filled vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE.
R1,C9,C10 on bottom TO ROSA place C5 on bottom of board underneath C6 C6 C1 PIN filled vias to GND C2 double-vias to reduce inductance to supply and GND place C7 on bottom of board C8 underneath C8 C3 OUTP
1
exposed pad
NIN C4
OUTN transmission lines same width as AC coupling caps to reduce reflections
~4mm
double-via to GND to reduce inductance
Via to C12, R2 on bottom Vias to bottom
Figure 9. Recommended ADN2892 PCB Layout
Rev. PrA| Page 10 of 12
Preliminary Technical Data OUTLINE DIMENSIONS
3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION 1.50 REF
9 8
ADN2892
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR 1.45 1.30 SQ* 1.15
13 12
16
BOTTOM VIEW
1
5
4
0.25 MIN
Figure 10. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 x 3 mm Body (CP-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN2892ACP-RL ADN2892ACP-RL7 Temperature Range -40C to +95C -40C to +95C Package Description 16-LFCSP 16-LFCSP Package Option CP-16-2 CP-16-2
Rev. PrA | Page 11 of 12
ADN2892 NOTES
Preliminary Technical Data
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04986-0-6/04(PrA)
Rev. PrA| Page 12 of 12
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